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PDF) Concurrent Self-Test with Partially Speciﬁed Patterns For Low Test Latency and Overhead

PDF) Concurrent Self-Test with Partially Speciﬁed Patterns For Low Test Latency and Overhead

PDF) Delay-Insensitive Cell Matrix.

PDF) Delay-Insensitive Cell Matrix.

PDF) A Context-Aware Meeting Room: Mobile Interaction and Collaboration Using Android, Java ME and Windows Mobile

PDF) A Context-Aware Meeting Room: Mobile Interaction and Collaboration Using Android, Java ME and Windows Mobile

PDF) UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations

PDF) UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations

NiDS2022 (Novel & Intelligent Digital Systems) - ATHENS

NiDS2022 (Novel & Intelligent Digital Systems) - ATHENS

PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences

PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences

PDF) Survival analysis for modeling critical events that communities may undergo in dynamic social networks

PDF) Extending Internet into Space – ESA DTN Testbed Implementation and Evaluation

PDF) Extending Internet into Space – ESA DTN Testbed Implementation and Evaluation

PDF) Detection of Delay Faults in Memory Address Decoders

Education and Information Technologies | Home

Education and Information Technologies | Home

PDF) A domain-specific approach for software development on Manycore platforms

PDF) A domain-specific approach for software development on Manycore platforms

PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences

PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences

IVML > People > Phivos Mylonas

PDF) Modeling and Simulation of Efficient March Algorithm for Memory Testing

PDF) Modeling and Simulation of Efficient March Algorithm for Memory Testing

PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences

PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences

PDF) A Closed-Loop Approach for Improving the Wellness of Low-Income Elders at Home Using Game Consoles

PDF) A Closed-Loop Approach for Improving the Wellness of Low-Income Elders at Home Using Game Consoles

PDF) On the generation of pseudo-deterministic two-patterns test sequence with LFSRs.

PDF) On the generation of pseudo-deterministic two-patterns test sequence with LFSRs.

PDF) Test pattern generation based on arithmetic operations

PDF) Test pattern generation based on arithmetic operations

PDF) Memory testing with a RISC microcontroller

PDF) Memory testing with a RISC microcontroller

Education and Information Technologies | Home

Education and Information Technologies | Home

Education and Information Technologies | Home

Education and Information Technologies | Home

PDF) On the Generation of Functional Test Programs for the Cache Replacement Logic

PDF) On the Generation of Functional Test Programs for the Cache Replacement Logic

PDF) Multimode scan: Test per clock BIST for IP cores

PDF) Multimode scan: Test per clock BIST for IP cores

PDF) Symmetry Measure for Memory Test and Its Application in BIST Optimization

PDF) Symmetry Measure for Memory Test and Its Application in BIST Optimization

PDF) Accumulator-Based Weighted Pattern Generation.

PDF) Accumulator-Based Weighted Pattern Generation.

PDF) Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

PDF) Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

PDF) Test Embedding with Discrete Logarithms

PDF) Test Embedding with Discrete Logarithms

Latest Award Winners

Latest Award Winners

Steffen Tarnick's research works | Universität Potsdam, Potsdam and other places

PDF) Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata

PDF) Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata

PDF) New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults

PDF) New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults